The present invention relates to a protective pattern of a semiconductor device.
Typically, plural integrated circuits are formed on a wafer in a semiconductor device manufacturing process. The wafer is die-cut into individual IC chips (see Japanese Patent Application Laid-Open No. 2002-261050). Plural semiconductor devices are manufactured from one wafer.
A stress is applied to a chip at die-cut. The stress causes cracks (chip cracks). A protective pattern is provided around the circuit element region of the chip to prevent cracks from being spread into the circuit element region.
The protective pattern has an element region formed on a substrate (wafer), an element separation region, a dummy gate layer, a dummy wiring layer, and a passivation layer formed on them. A fewer number of stacked substances on the substrate are preferred on a region (dicing line) to perform die-cut. The passivation layer is removed on the dicing line side of the protective pattern.
The stress applied to the chip at die-cut tends to be strong in a location where the material and the configuration are changed. Cracks are caused in a location near the circuit element region, which influences the circuit element region to be protected. To reduce the influence, the protective pattern is increased so that the crack caused location is as far as possible from the circuit element region. In such technique, the chip size is increased and the number of chips which can be manufactured from one wafer is reduced.
There has been known a configuration provided with a stacked structure in which plural contacts and wiring layers are stacked on the dicing line side rather than at the end of the passivation layer. The stacked structure acts as a stopper preventing the progress of cracks and pattern separation. In such configuration, the area of the protective pattern is increased due to the arrangement of the stacked structure. As stated above, the chip size is increased and the number of chips which can be manufactured from one wafer is reduced.